Design systematic defects pose critical yield bottleneck in the semiconductor design process, especially at the beginning phase of yield ramping for a product. One of the most effective ways to detect systematic via failure is by electron beam (eBeam) voltage contrast (VC) die-to-database (D2DB) inspection, which compares the voltage contrast of vias in silicon to the design. It can effectively detect an open via, a missing pattern, and critical dimension (CD) shrinkage. However, both real defective vias and electrically floating vias show up as dark voltage contrast (DVC) and cannot be separated from real DVC defects.
A need therefore exists for methodology and apparatus enabling separation of real DVC via defects from nuisance after eBeam VC die comparison inspection.